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Attiny85

ATTINY and Arduino as ISP

nano_to_attiny_bb.png

AvrDude

avrdude -c stk500v1 -p att85 -P /dev/ttyACM0 -b 19200 -U flash:w:blink.hex

-c m328p -p t85

avrdude -c <programmer> -p <device> -P <serial port> -b <baud rate> -U <memtype>:<r|w|

ATTINY85 schematics

  PCINT5/RESET/ADC0/Dw/PB5 ---*--- VCC
      PCINT3/CLKI/ADC3/PB3 ------- PB2 SCK/ADC1/T0/PCINT2
           PCINT4/ADC2/PB4 ------- PB1 MISO/AIN1/OC0A/INT0/PCINT1
                       GND ------- PB0 MOSI/AIN0/OC0B/PCINT0

Attiny Basis

Code example


#include <avr/io.h>

DDRB |= (1 << PB3); /* PB3 as OUTPUT */
DDRB &= ~(1 << PB3) /* PB3 as INPUT */

/* If DDRB is configured as OUTPUT */

PORTB |= (1 << PB3); /* PB3 HIGH */
PORTB &= ~(1 << PB3); /* PB3 LOW */

/* If DDRB is configured as INPUT */

PORTB |= (1 << PB3); /* PB3 PULL-UP activated */
PORTB &= ~(1 << PB3); /* PB3 PULL-UP deactivated */

Analog Input

ADMUX ADC Multiplexer Selection Register

ADC : Analog to Digital Conversion

Bit 7 6 5 4 3 2 1 0
0x07 REFS1 REFS0 ADLAR REFS2 MUX3 MUX2 MUX1 MUX0

REFS[0:2]

ADLAR: Left adjust result

MUX: Input channel selection:

Single ended input

Differential input

ADCSRA ADC Control and Status Register A

Bit 7 6 5 4 3 2 1 0
0x06 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS[2:0]

Code Example

ADMUX |= (1 << REFS0);   //sets reference voltage to internal 1.1V
ADMUX |= (1 << MUX0);    //set ADC3...
ADMUX |= (1 << MUX1);    //as analog input channel.
ADMUX |= (1 << ADLAR);   //left adjusts for 8-bit resolution
ADCSRA |= (1 << ADEN)  //turn on ADC
ADCSRA |= (1 << ADPS1) // ADC prescaler
ADCSRA |= (1 << ADPS0) // division 8 (011)
ADCSRA |= (1 << ADSC);   //start conversion
analogData = ADCH;       //read data

Analog Output (PWM)

TCCR0A

Bit 7 6 5 4 3 2 1 0
0x2A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00

COM0A[1:0]

Compare match output A

COM0B[1:0]

Compare match output B

COM0(A/B)[1:0] settings non PWM mode

COM0(A/B)[1:0] settings FAST PWM mode

COM0(A/B)[1:0] settings Phase Correct PWM mode

Waveform Generation Mode Bit Description

Mode WGM02 WGM01 WGM00 Timer/Counter Mode of Operation TOP Update of OCRx at TOV Flag Set on
0 0 0 0 Normal 0xFF Immediate MAX
1 0 0 1 PWM, Phase Correct 0xFF TOP BOTTOM
2 0 1 0 CTC OCRA Immediate MAX
3 0 1 1 Fast PWM 0xFF BOTTOM MAX
4 1 0 0 Reserved - - -
5 1 0 1 PWM, Phase Correct OCRA TOP BOTTOM
6 1 1 0 Reserved - - -
7 1 1 1 Fast PWM OCRA BOTTOM TOP

TCCR0B

Bit 7 6 5 4 3 2 1 0
0x33 FOC0A FOC0B - - WGM02 CS02 CS01 CS00

FOC0A

Force Output Compare A

FOC0B

Force Output Compare B

WGM02

Waveform Generation Mode

CS[2:0] Clock Select

Code example

DDRB |= (1 << DDB0); // set PB0 as output
TCCR0A |= (1 << COM0A1); // set compare match on PB0
TCCR0A |= (1 << COM0A0); // set compare match on PB0
TCCR0A |= (1 << WGM01);  // enable Fast PWM
TCCR0A |= (1 << WGM00);  // enable Fast PWM
TCCR0B |= (1 << WGM02);  // enable Fast PWM
TCCR0B |= (1 << CS10);  //  set clock whithout prescaler
OCR0A  |= (1 << 7)  // set duty cycle to 128 aka 50%
/* This can be changed in loops or interupt to whatever is needed
   In order to change the duty cycle
*/

Interupts

note

sei() Enable all interrupts cli() Disable all interrupts

Code Example

ISR(PCINT0_vect)
{
    //do something
}

Photoresitance Montage et Code

Modele: GL5539 - Resistance a la lumiere: 50-100KΩ - Resistance à 0 lux: 5MΩ 

 ------------
 |           |

Vcc –-- R1 |

–N
---P

–------ R2 –N

- Vcc
- -
- -

–---------- - 

Calcul de pont diviseur avec une photo-résistance

def t_div(u, r2, r1):
    return u*r2/(r1+r2)

def light(val):
    return val > 0.7


for a in range(30):
    a = float(a)
    f = float(a/10)
    r1 = 1*(10**6)
    vals = [5, 3, 2, 1.5, 1, 0.9]
    vals = [val*10**6 for val in vals]
    print(f, [(light(t_div(f, r1, val)), val/10**6) for val in vals])

La valeur optimale semble être 1MΩ pou r1: (2.6, [(False, 5), (False, 3), (True, 2), (True, 1.5), (True, 1), (True, 0.9)]) (2.7, [(False, 5), (False, 3), (True, 2), (True, 1.5), (True, 1), (True, 0.9)]) (2.8, [(False, 5), (False, 3), (True, 2), (True, 1.5), (True, 1), (True, 0.9)]) (2.9, [(False, 5), (True, 3), (True, 2), (True, 1.5), (True, 1), (True, 0.9)])

Puisque sur une plage de 2.9 à 2.6 volts on détecte une chute de résistance jusqu'a 3MΩ

Code Attiny85 

   .   . vcc
   .   . pb2 -- PNP
   .   .

gnd. . pb0 – buzzer 

#include <avr/io.h>
#include <avr/sleep.h>
#include <avr/power.h>
#include <avr/wdt.h>
#define F_CPU    1000000

volatile int counter = 0

void setup(void){
    cli(); // turn off interupts
    MCUSR = 0; // cleanup register
    WDTCR = (1<<WDCE)|(1<<WDE); // write logical 1 to WDCE and WDE
    WDTCR = 0;

    WDTCR = (1<<WDIE) | (1<<WDP2) | (1<<WDP0);
    sei();
      }

void check_ldr(void){
    if (PINB & (1<<PINB1) )
      counter++;
    else
      counter=0;
      DDRB |= (0 << DDB0); //disable PB0 as output to end the buzzer

  }

void check_counter(void){
    if (counter > 10)
      DDRB |= (1 << DDB0); // play that noise
}


void setup_ldr(void){
    DDRB &= ~(1 << PB2) /* PB2 as INPUT */
    PORTB |= (1 << PB2); /* PB2 PULL-UP activated */
    /* PORTB &= ~(1 << PB2); PB2 PULL-UP deactivated See what work best */
    TCCR0A |= (1 << COM0A1); // set compare match on PB0
    TCCR0A |= (1 << COM0A0); // set compare match on PB0
    TCCR0A |= (1 << WGM01);  // enable Fast PWM
    TCCR0A |= (1 << WGM00);  // enable Fast PWM
    TCCR0B |= (1 << WGM02);  // enable Fast PWM
    TCCR0B |= (1 << CS02);  //  set clock whith  1024 prescaler
    OCR0A  |= (1 << 6) | (1 << 5) | (1 << 4) | (1 << 2); // 116
    /* 1mhz/1024/(116/256) ~ 440hz aka A  */

}

ISR(WDT_vect) {
    setup_ldr();
    check_ldr();
    check_counter();
    WDTCR |= (1<<WDIE);  //re-enable watchdog timer after the check occurs
}